## Design 4-Bit Binary Counter with Parallel Load using Nanometric Technique

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One of the commonly used counters is thea 4-bit presettable up-down counter. This counter can be parallel loaded or preset 4 bit binary counter with parallel load the initial value. It has two clocks, one for up-counting and the other for down-counting. The load input is used for presetting the counter and the clear input will reset it.

Connect the outputs to the lamps and the inputs to the switches. Connect 4 bit binary counter with parallel load chip for up counting. Connect the clock output to the up input and draw the timing diagram.

Does the counter trigger on the positive or negative edge of the clock? What is the duration of the carry out pulse? Activate the clear and keep the up clock going. Set the inputs toand activate the load. Does clear and load supersede the count?

The Q output of a D flip-flop is delayed one clock cycle from the input. Thus, if several D flip-flops are connected so that the output of one flip-flop is connected to the input of the next flip-flop, the input to the first flip-flop can be propagated to the next in successive clock cycles. Such an arrangement is called a shift-register. Connect lamps to the Q output of each flip-flop.

Demonstrate this shift register to your instructor. The is a 4-bit universal shift register, i. The initial value can be preset like the counter. Unlike the counter though, the has only a single clock. The Sl and S0 control lines as shown can control the operation of the chip:. During parallel load, the values of the parallel inputs A, B, C and D are latched into the register.

All these operations are synchronized with the leading edge of the clock. A lo on clear will reset the register regardless of the clock and control line settings. Connect the outputs to the lamps; 4 bit binary counter with parallel load parallel inputs, controls and serial inputs to the switches; and the clock to the input. Preset the register to and connect as a circulating right shift register.

Draw the truth table. In digital control logic it is sometimes necessary to generate a multiple phase clock from a single clock as shown:. One way to accomplish this is by designing a 2-bit counter and decoding each stage. An alternate way is to load a single '1' in a 4-bit shift register and allow it to circularly shift right.

This is called a ring counter. Modify your ring counter such that it is self starting, i. Demonstrate this to your instructor. Skip to Main Content. Binary Counters and Shift Registers Objective: To study counter and shift register chips Binary Counter: Repeat a for the down counter. The Sl 4 bit binary counter with parallel load S0 control lines as shown can control the operation of the chip: Repeat 2c for the circulating left shift operation. In digital control logic it is sometimes necessary to generate a multiple phase clock from a single clock as shown: