PHY-Layer Authentication Using Duobinary Signaling for Spectrum Enforcement

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Year of fee payment: A binary signal is transmitted through an electrical backplane, and the received signal is interpreted as a duobinary signal. In order to ensure that the received signal can be properly interpreted as a duobinary signal, the data signal is preferably filtered prior to being interpreted. The filter is preferably designed such that the combination of filter and the backplane approximates a binary-to-duobinary converter.

In one embodiment, an FIR-based equalizing filter is applied to the data signal prior to transmission to emphasize the high-frequency components and flatten the group delay of the backplane. The resulting, received duobinary signal is converted into a binary signal by 1 splitting the duobinary duobinary signalling scheme, 2 applying each copy to a suitably thresholded comparator, and duobinary signalling scheme applying the comparator outputs to a suitable e.

The transmission system enables high-speed data e. The invention relates to signal processing, and, in particular, to the transmission of e. Gigahertz-speed data rates are required in core optical products such as high-speed routers and cross-connect switches.

Many such large-scale systems require the routing of hundreds duobinary signalling scheme thousands of signals in a small area using little power and for low cost. Typically, this routing occurs on a multi-layer board called a high-speed backplane. Maintaining signal integrity for gigahertz-speed line rates on this structure is very difficult, and has resulted in an important field of study.

There are several approaches being pursued by many vendors to maintain backplane signal transmission integrity. These techniques fall into basically two categories: Passive solutions incorporate the use of high-quality microwave substrate materials, innovative via hole techniques, and new connector technology. While these techniques can duobinary signalling scheme address the transmission problem, the use of costly microwave substrates and special high-bandwidth backplane connectors are often required.

Moreover, very long trace lengths may still result in less-than-acceptable duobinary signalling scheme characteristics. Active solutions include adaptive equalization, pre-emphasis, PAM-4, and combinations thereof. Although these solutions can provide excellent performance even for long trace lengths, power consumption and cost can be issues. Typically, active solutions that provide equalization or pre-emphasis must correct the entire NRZ data bandwidth.

The problem is that, for many low-quality transmission systems, the frequency-response roll-off is severe, and the use of via holes on thick backplanes results in nulls in the frequency range of interest. Equalization or pre-emphasis through duobinary signalling scheme requires the use of duobinary signalling scheme networks, and the resulting correction will be very sensitive to temperature and parameter variations.

One solution to the problem of poor high-frequency response is to compress the bandwidth using multi-level duobinary signalling scheme. PAM-4 is currently being used with equalization by some vendors to address this problem. Although this technique has been shown to provide very good performance even over long traces, these circuits are typically complex, leading to difficulty providing dense integration and significantly increased power consumption relative to standard NRZ signaling.

Problems in the prior art are addressed in accordance with the principles of the invention by duobinary signalling scheme electrical duobinary signaling for electrical backplanes to provide both bandwidth reduction and simplification of implementation suitable for high-scale integration. The idea behind the duobinary signaling architecture of the present invention is to reshape the complex data spectrum from the duobinary signalling scheme such that the resulting waveform available at the receiver after traveling through an electrical backplane is a duobinary signal.

Other aspects, features, and advantages of the invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements.

Binary data transmitter provides a non-return-to-zero NRZ binary data stream to be transmitted through a duobinary signalling scheme. Duobinary precoder manipulates data bits in the NRZ binary data stream so that, at the receiver, an error in a duobinary signalling scheme bit is not dependent on the previous bit, as described in Digital Transmission Systemsby David R.

Smith, Van Nostrand Reinholdpp. Equalizing filter reshapes both the amplitude and phase of the complex spectrum of the signal prior to being transmitted through electrical backplane Equalizing filter is designed such that the combination of filter and backplane effectively operates as a binary-to-duobinary converter. In other words, when an NRZ binary data signal is filtered by equalizing filter and then transmitted through electrical backplanethe resulting signal presented to duobinary-to-binary converter looks like a duobinary data signal corresponding to duobinary signalling scheme original NRZ binary data signal.

A signal corresponding to one of these levels i. A duobinary signal is typically generated from a corresponding binary signal using certain transformation rules. Although both signals carry the same information, the bandwidth of the duobinary signal may be reduced by a factor of two compared to that of duobinary signalling scheme binary signal at the expense of signal-to-noise ratio.

More specifically, when i is odd, the polarity of b m is the same as the polarity of b m-i ; and, when duobinary signalling scheme is even, the polarity of b m is the opposite of the polarity of b m-i. Reconstruction of a k from a known b k is relatively straightforward. As a result, as indicated in the graphical portions of FIG. The resulting combined response of equalizing filter and electrical backplanealso shown in FIG.

Since the duobinary duobinary signalling scheme spectrum has a null at duobinary signalling scheme half the bit rate, the amount of high-frequency emphasis is greatly reduced when compared to emphasizing uncoded NRZ data. As such, the fact that the spectral components of concern are below half the bit rate provides a significant advantage. Although equalizing filter is preferably implemented using a finite impulse response FIR filter, any other suitable filter implementation could also be used.

Moreover, although equalizing filter is shown in FIG. Equalizing filter preferably reshapes both the amplitude and phase of the complex data spectrum so that the data presented to duobinary-to-binary converter is in fact duobinary data. Duobinary signalling scheme can be accomplished using a filter that emphasizes the high-frequency components and flattens the group delay of the backplane. In general, the use of Equation 2 may result in a filter that has many coefficients.

For a high-speed, discrete-time implementation, this is not desirable. Implementing equalizing filter using a discrete-time FIR filter placed at the data transmitter can accomplish this task using a minimal number of gates and analog functionality. Although this is not the most general formulation for equalizing filterit is believed to be adequate for most cases, while providing simplicity. In other implementations, for example, the filter could have more than two taps.

In particular, data source e. Selector selects one of its inputs based on a tap selector control signal The selected input is applied duobinary signalling scheme attenuatorwhich attenuates the selected input based on an attenuation selector control signal The resulting attenuated value is added to the original data stream at summing amp to generate the pre-emphasized output signal.

Tap selector control signal can select any duobinary signalling scheme of the inputs t 0. The delay selected by selector depends on duobinary signalling scheme impulse response of the channel.

In this way, FIR pre-emphasis filter a can add a delayed-and-scaled replica of the original signal to the original signal, so as to realize the response from Equation 1.

Note that an inverting amplifier is not needed to realize a minus sign in Equation 1 for negative filter coefficients. Since the input data is purely digital at this point in the system, the inverted data stream can be used to accomplish the same effect. Depending on the implementation, the FIR filter may be adaptive or it may have fixed tap delays and amplitudes.

Filter b comprises data source flip-flopsumming ampdelays - 1 duobinary signalling scheme - 2and 6-dB attenuator As indicated in FIG. When implemented in hardware, converter can be realized using a balanced-input, exclusive-OR gate, where the thresholds are set appropriately. In addition, converter can be adapted in a relatively straightforward fashion to work at even higher bit rates and lends itself to relatively easy incorporation into an integrated device e.

As shown in FIG. Copy s a t is applied to the inverting input of a first comparator awhose non-inverting input receives a first threshold voltage V 1. Similarly, copy s b t is applied to the non-inverting input of a second comparator bwhose inverting input receives a second threshold voltage V 2.

The output x of each comparator is a digital signal generated as follows. Duobinary signalling scheme signal trace shown in FIG. Table I illustrates the operation of converter configured in accordance with FIG. Converter is similar to converter of FIG. One difference between converters andis duobinary signalling scheme, in convertersignal copy s a t is applied to the non-inverting input of comparator aand threshold voltage V 1 is applied to the inverting input of duobinary signalling scheme a.

The present invention provides backwards compatibility for certain applications in which duobinary signalling scheme binary data rate is one-fourth or less than the duobinary data rate. In this configuration, the output of comparator b of FIG. In this configuration, the output of comparator b is always one. In this configuration, the output of comparator a of FIG. In this configuration, the output of comparator a is always one. Each of these configurations effectively turns off one of the comparators of Duobinary signalling scheme.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. The present invention can implemented for either analog or digital signal processing. A logic gate may be implemented as a combination of duobinary signalling scheme logic elements as known in the art. The present invention has been described in the context of a transmission system having a duobinary precoder, an equalizing pre-emphasis filter before the electrical backplane, and a duobinary-to-binary converter after the electrical backplane.

The invention is not so limited. Depending on the particular application the duobinary precoder could be optional. Similarly, as previously mentioned, an equalizing post-emphasis filter could be implemented after the electrical backplane in addition to or instead of the pre-emphasis filter. Moreover, in applications in which the transfer function of the electrical backplane by itself sufficiently approximates that of a binary-to-duobinary converter, the transmission system could, in theory, be implemented without any equalizing filtering, either before or after the backplane.

Furthermore, there may be applications in which the resulting duobinary signal does not need to be converted back to a binary signal. Various modifications of the described embodiments, as duobinary signalling scheme as other embodiments of the invention, which are apparent duobinary signalling scheme persons skilled in the art to which the invention pertains are deemed to lie within the principle and scope of the invention as expressed in the following claims.

Although the steps in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of duobinary signalling scheme steps, those steps are not necessarily intended to be limited to being implemented in that particular sequence.

A method for processing a data signal, comprising: The invention of claim 1further comprising precoding a binary data signal, wherein the data signal transmitted through the electrical backplane is based on the precoded binary data signal.

The invention of claim 1 duobinary signalling scheme, further comprising filtering the data signal prior to interpreting the data duobinary signalling scheme as the duobinary duobinary signalling scheme signal.

The invention of claim 3wherein the filtering is implemented before transmission through the electrical backplane. The invention of claim 3wherein the filtering comprises equalizing filtering.

The invention of claim 3wherein the filtering is designed to emphasize high-frequency components in the data signal and flatten group delay of the electrical backplane.

The invention of claim 3wherein the filtering is implemented using an FIR filter. The invention of claim 3wherein the filtering:

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